High speed networks generate problems of performance and hardware component integration at the physical interface of the networking equipement connected to their network links. In the network link physical interface the data flows exchanged at media speed are processed. This media speed process comprises controlling operations such as scrambling and descrambling, error code checking (most of them implying Cyclic Redundancy Checking calculations) etc . . . These operations require complex logics and need to be optimized to sustain high speeds.
FIG. 1 illustrates the physical interface sublayers necessary to connect equipment to the network. For each network link (5) a first physical interface sublayer (40) including connectors (43), magnetics (42), Phased Locked Loops and transceivers (41) is dependent on the type of medium (copper lines, optical fibers). The input bit stream data flows are then processed in the upper sublayer (30) which provides the functions of frame units delineating, descrambling, CRC checking in the Receive side and CRC generation, scrambling and bit stream encoding in the Transmit side. In the Receive side, the upper sublayer (30) receiving media speed data flow sends delineated frame units on an internal bus (20) where further processing will be perfomed in the network equipment. The data is sent to the internal bus at a different rate from the data reception rate which is media speed of the input links.
The ATM Forum Technical Committee has published a Physical Interface specification for 25.6 Mb/s over Twisted Pair Cable for ATM network node connection to a private ATM network equipement following the User Network Interface (UNI). This specification incorporated herein by reference, describes the media dependant sublayer (so called PMD, Physical Media Dependent sublayer) and the upper sublayer, the Transmission Convergence (TC) sublayer. FIG. 2 illustrates the process performed in the TC sublayer in the Receive side. The bit stream data flow coming from the PMD sublayer is first decoded by an NRZI (Non Return to Zero Inverted) decoder (50), and deserialized as a five bit data flow to be, in a next step (52) decoded from 5 bits to 4 bits to form a data nibble, the symbols are aligned, the cell delineation being supported by the X.sub.-- X and X.sub.-- 4 escape commands identified and transmitted, octet aligned (56); the nibbles are then descrambled (54), using the output of the PRNG (Pseudo-Random Number Generator) which is itself reset by the X.sub.-- X signal; the cell headers are checked (56) by CRC calculations. The cells are sent to the internal bus of the ATM forwarder sublayer responsible for the ATM processing and routing. In the Transmit side the cell stream is scrambled, converted into nibbles and coded into a bits stream sent to the PMD sublayer.
The physical interface sublayer such as the TC sublayer for ATM networks requires for its hardware implementation the use of logic circuits and static memories which are today the most used components for high speed networks. The problem encountered by the hardware designers to optimize the hardware implementation of these functions is the limited space and the cost of components.
The problem becomes even more crucial as, with the development of high speed network equipment for campus networks, users require more and more hardware concentration. In the IBM TURBOWAYS 8282 ATM workgroup concentrator as well as in the VIRATA switch of ATM ltd, the Transmission Convergence ATM sublayer of the 25.6 Mb/s physical interface for one port is provided on one chip.
With the emerging request for more and more concentration, there is a need in the networking industry for integration of the multiport physical interface layer hardware implementation. This support for multiport attachment implies a higher complexity with the functions of multiplexing/demultiplexing of data flows. The hardware structure, in the view of integration, needs to maximize the sharing of logics and memories between port data flows. Moreover, some specific components such as imbedded static RAMs allow hardware integration because of their high density; by the way, this technology raises new problems for shared accesses. These memories cannot be simultaneously accessed by several resources, this is not the case when registers are used for sharing of data. Finally, the implementation of network physical interface has to take into account for resources sharing the different input and output data flow rates. In the Receive side the input multiport data flows are at media speed while the output multiplexed data flow is sent to one internal bus of the network equipment with a rate imposed by an external control unit.